1. Field of Invention
The present invention relates to an inspection method for a semiconductor device. More particularly, the present invention relates to a wafer level burn-in for static random access memory (SRAM).
2. Description of Related Art
Static random access memory (SRAM) is frequently used in high-speed data access circuits such as the cache memory of a central processing unit (CPU). Because the fabrication of SRAM involves a large number of complicated steps, a burn-in testing of the SRAM product is necessary before shipment to customers. A burn-in test is a quick way of assessing the quality of an electronic product by subjecting the product to particularly stringent operating conditions. Any products that are not up to standard and likely to fail can be determined through the test and subsequently removed. Burn-in testing is conducted by applying a voltage at the gate terminal of a metal-oxide-semiconductor (MOS) transistor within an SRAM cell so that quality of the gate dielectric layer can be assessed, while finding out the SRAM cell with a defective gate dielectric layer. Furthermore, a potential is frequently applied to neighboring conductive lines so that short-circuiting can be found. The particular chips that cannot pass such tests are removed. In general, most short-circuiting problems occur due to faulty metallic interconnections. The most common reason for such short-circuiting includes an inferior glue layer surrounding a metal via so that metallic material is spread out. Hence, a non-planar substrate is produced leading to inaccuracy in subsequent patterning of conductive lines.
Conventionally, the burn-in of SRAM chips is conducted after packaging. However, the whole package has to be discarded once burn-in test fails. Due to the high level of integration in each SRAM product, cost of producing a package is also very high. Hence, throwing away a packaged product is a highly uneconomical move. Moreover, the conventional burn-in method includes switching various word lines and bit lines of a SRAM chip on and off sequentially. Hence, the burn-in process is rather slow and may take a few hours to complete. Furthermore, burn-in time also increases with the level of integration inside the SRAM chip.